Registers at call
Return Registers
Notes
ROM BASIC Functionality
Supported Models
Registers at call:
AH = C9h
Return Registers:
CF set on error
AH = status
(80h, 86h = Function not supported)
CF clear if successful
AH = 00h
CH = CPU Family (see Family table below)
CL = If CX = 030xh (386DX) or 230xh (386SX) then CL = Stepping
Otherwise the 4 highest-order bits are the CPU Model, lowest-order the CPU stepping reference
Table of CPU Family values (Note: these are only Intel and IBM values, AMD, Cyrix, and other CPU manufacters have other stepping information):
CX = 030xh: 386DX class
CL = 00h: A Step
CL = 03h: B1 Step
CL = 04h: C Step
CL = 05h: D0 Step
CL = 08h: D1, D2, E1, or F0 Step
CX = 0340h: Intel RapidCAD
CH = 04h: 486 class
CL = 0xh: 486DX-25, 486DX-33, or some 487SX (single clock speed with onboard FPU), with 8Kb Write-Through L1 cache
00h: Step A0 or A1
01h: Step B2 through B6
02h: Step C0
03h: Step C1
04h: Step D0
CL = 1xh: 486DX-50 or later 486DX-33 (single clock speed with onboard FPU), with 8Kb Write-Through L1 cache
10h: Step cA2 or cA3
11h: Step cB0 or cB1
13h: Step cC0
14h: Step aA0 or aA1
15h: Step aB0
CL = 2xh: 486SX-16, 25, or 33 (single clock speed without onboard FPU) or some 487SX, with 8Kb Write-Through L1 cache
20h: Step A0
21h: Step B0
22h: Step D
23h: Step gAx
24h: Step D0
27h: Step cA0
28h: Step cB0
2Ah: Step E, aA0, or aA1
2Bh: Step aB0 or aC0
CL = 3xh: 486DX2-50 or 66 (clock doubled internal speed with FPU) with 8Kb Write-Through L1 cache
32h: Step A0 through A2
33h: Step B1
34h: Step aA0 or aA1
35h: Step aB0 or aC0
36h: Step A CPUID 0470h CPU in Write-Through mode
CL = 4xh: 486SL-25 or 33 (low-power 486DX in PQFP packaging) with 8Kb Write-Through L1 cache
40h: Step A
41h: Step A
CL = 5Bh: 486SX2-50 (clock doubled internal speed without FPU) with 8Kb Write-Through L1 cache
CL = 70h: 486DX2-66 with 8Kb Write-Back L1 cache
CL = 8xh: 486DX4-75 or 100 with 16Kb Write-Through L1 cache (clock tripled internally with onboard FPU)
80h: Step A
83h: Step A CPUID 0490h CPU in Write-Through mode
CL = 90h: 486DX4-75 or 100 with 16Kb Write-Back L1 cache, Step A
CH = 05h: Pentium class (many variants)
CH = 14h: 486 class Overdrives
CL = 80h: 486DX4-100 with 16Kb Write-Through L1 cache (clock tripled internally with onboard FPU), Step A
CH = 15h: Pentium class 486 Overdrives
CL = 31h: 63MHz POD, Step B1/B2
CL = 32h: 63 or 83MHz POD, Step C0
CH = 23h: 386SX class
CL = 04h: A0 Step
CL = 05h: B Step
CL = 08h: C, D, or E Step
CH = A3h: IBM 386SLC class
CL = 01h: Only known variant
CH = A4h: IBM 486SLC class
CL = 21h: 486SLC2, Step A
CL = 22h: 486SLC2, Step B
CL = 39h: 486SLC3, Only known variant
Notes:
The BIOS must save the CPU Reset Signature (a function only present on 386SX/386DX or later CPUs) at startup in order to support this call. Microchannel PS/2s use Extended CMOS to store the values at offset 190h and 191h, with the exception of the PS/2 Model 55SX, which uses EBDA (Extended BIOS Data Area) offsets B6h and B7h. ISA PS/2 models with 386SX+ CPUs use EBDA offsets EEh and EFh. The PS/2 Model P70 with the "old" 20MHz-only planar having the BIOS EPROM pair 65X1565 / 65X1566 does store the correct values in Extended CMOS, but does not support INT 15h, Function C9h.
ROM BASIC Functionality:
To get the CPU class and stepping for use in the chart above - retrieving values is complicated by where the system stores the data.
For the models with Extended CMOS, use this routine:
OUT &H74, &H90
OUT &H75, &H01
ClassCPU = INP(&H76)
OUT &H74, &H91
OUT &H75, &H01
SteppingCPU = INP(&H76)
For the models using the Extended BIOS Data Area (EBDA), find the EBDA segment by the ROM BASIC routine at INT 15h, Function C1h, then use this routine according to model:
DEF SEG=[EBDA Segment]
ClassCPU = PEEK(&H[either 'B7' or 'EE', depending on model])
SteppingCPU = PEEK(&H[either 'B6' or 'EF', depending on model])
All code is with the assumption that the data storage area for that model have been unmolested since booting the system.
Supported Models, CPU Family, and CPU Stepping Location:
| Model: | CPU Family Data: | CPU Model/Stepping Data |
| Model 25SX | [EBDA](9FC0h):EEh | [EBDA](9FC0h):EFh |
| Model 33 'E' | [EBDA]:EEh | [EBDA]:EFh |
| Model 35SX | [EBDA]:EEh | [EBDA]:EFh |
| Model 40SX | [EBDA]:EEh | [EBDA]:EFh |
| Model L40SX | [EBDA](9F40h):EEh | [EBDA](9F40h):EFh |
| Model N51SX | Extended CMOS 0190h | Extended CMOS 0191h |
| Model N51SLC | Extended CMOS 0190h | Extended CMOS 0191h |
| Model 53SLC2 | Extended CMOS 0190h | Extended CMOS 0191h |
| Model 55SX | [EBDA](9FC0h):B7h | [EBDA](9FC0h):B6h |
| Model 55LS | Extended CMOS 0190h | Extended CMOS 0191h |
| Model 55LS 486 | Extended CMOS 0190h | Extended CMOS 0191h |
| Model 56SX | Extended CMOS 0190h | Extended CMOS 0191h |
| Model 56SLC | Extended CMOS 0190h | Extended CMOS 0191h |
| Model 56 486SLC2 | Extended CMOS 0190h | Extended CMOS 0191h |
| Model 56 486SLC3 | Extended CMOS 0190h | Extended CMOS 0191h |
| Model 57SX | Extended CMOS 0190h | Extended CMOS 0191h |
| Model 57SLC | Extended CMOS 0190h | Extended CMOS 0191h |
| Model 57 486SLC2 | Extended CMOS 0190h | Extended CMOS 0191h |
| Model 57 486SLC3 | Extended CMOS 0190h | Extended CMOS 0191h |
| Model CL57SX | Extended CMOS 0190h | Extended CMOS 0191h |
| Model 65SX | Extended CMOS 0190h | Extended CMOS 0191h |
| Model 70 | Extended CMOS 0190h | Extended CMOS 0191h |
| Model P70 | Extended CMOS 0190h (see note above) | Extended CMOS 0191h (see note above) |
| Model P75 | Extended CMOS 0190h | Extended CMOS 0191h |
| Model 76/76i/76s | Extended CMOS 0190h | Extended CMOS 0191h |
| Model 77/77i/77s | Extended CMOS 0190h | Extended CMOS 0191h |
| Model 80 | Extended CMOS 0190h | Extended CMOS 0191h |
| Model 85 | Extended CMOS 0190h | Extended CMOS 0191h |
| Model 90 | Extended CMOS 0190h | Extended CMOS 0191h |
| Model 95 | Extended CMOS 0190h | Extended CMOS 0191h |
| PC Server 500 | Extended CMOS 0190h | Extended CMOS 0191h |