Registers at call
Return Registers
Notes
Supported Models
Registers at call:
AH = C8h
AL = Subfunction
00h: Disable both caches (or 90/95/500,
disables L1 cache)
01h: Enable both caches (or 90/95/500, Enables
L1 cache)
Models 90/95/500 only
02h: Disable L2 cache
03h: Enable L2 cache
04h: Disable both caches
05h: Enable both caches
06h: Return status of both caches
07h - FFh: Reserved
Return Registers:
CF set on error
CF clear if successful
AH = status (table below)
For subfunction 06h only
BH = Status of L2 cache
00h: Enabled
01h: Disabled or not
installed
BL = Status of L1 cache
00h: Enabled
01h: Disabled
Status table:
00h: operation successful
01h: Subfunction choice is invalid
02h: NV-RAM data is invalid
03h: cache test error (also listed as "cache
failed POST test")
04h: [90/95/500 only] cannot perform operation
requested due to state of other cache
05h: no L2 cache present
09h: CPU is in Protected Mode
80h: C8h function not supported
86h: C8h function not supported
Notes:
Support for this function is determined from the INT 15h Function C0h "Get Configuration" table, Feature Byte 2, Bit 3.
Supported Models:
Model 56SLC/486SLC2/486SLC3
Model 57SLC/486SLC2/486SLC3
Model 70 (-Axx model only)
Model 76/76i/76s
Model 77/77i/77s
Model 80 (-Axx model only)
Model 85
Model 90
Model 95
Server 500